The present invention relates to a semiconductor device fabrication method.
Conventionally, a NAND flash memory has been developed as a nonvolatile semiconductor memory. A memory cell transistor of this NAND flash memory has a structure in which a floating gate electrode formed on a semiconductor substrate via a tunnel insulating film and a control gate electrode formed on this floating gate electrode via an inter-electrode insulating film are stacked.
The NAND flash memory is formed by arranging memory cell transistors in a matrix. Between memory cell transistors adjacent to each other in a bit line direction, an inter-cell embedded insulating film is formed and embedded in slits (gaps) formed between these adjacent memory cell transistors.
In the NAND flash memory, a silicon nitride film is used as this inter-cell embedded insulating film. Since, however, the silicon nitride film has a high relative dielectric constant, the influence of a floating capacitance between memory cell transistors increases as the cell size decreases.
A reference concerning an inter-cell embedded insulating film formation method is as follows.
Reference 1: Japanese Patent Laid-Open No. 4-286321